The operation of previous dynamic random access memory circuits is described in U.S. Pat. No. 3,588,844 and 3,514,765 to Christeneon, U.S. Pat. No. 3,699,537 to Wahlstrom and U.S. Pat. No. 3,902,082 and 3,969,706 to Proebsting et al. As shown in the Wahlstrom and Proebsting Patents, it has been the practice to use sense amplifiers to detect voltage differentials on bit lines which have had memory cells connected thereto. The connection of the memory cell to the bit line changes the previously established voltage on the bit line to estabish the desired data state as a voltage differential on the bit lines. However, the voltage change on a bit line caused by the connection of a memory cell thereto is very small and the detection of such a small voltage change has presented a serious problem in the design of dynamic random access memories. A further problem is that electrical noise can be picked up by the bit lines and this noise can mask the desired voltage offset produced by a memory cell. Further, integrated circuit fabrication tolerances can result in unbalanced bit lines which also interfere with the reading of a memory cell.
In response to these problems, it has heretofore been the practice to incorporate a dummy cell with each bit line of the memory. The dummy cells are precharged to a given voltage state and are connected during each memory cycle to the nonselected bit line within each pair of bit lines. However, the inclusion of a large number of dummy cells together with their associated circuitry increases the size of the integrated circuit and adds to the circuit complexity.
In view of the above problems, there exists a need for a dynamic random access memory which operates in such a method so as not to require a dummy cell for each bit line while at the same time providing reliable identification of the voltage states stored in the memory cells.